What happened
The cited official source confirms 3 nanometre. This is a concise exam-oriented current-affairs point.
Verified fact: 3 nanometre. Remember the exact scheme, figure, year, institution or national milestone for objective examinations.
Chip design node size: 3 nanometre.
The cited official source confirms 3 nanometre. This is a concise exam-oriented current-affairs point.
Useful for SSC, Banking, Railway, UPSC and state-exam current-affairs revision.
Answer: 3 nanometre
Why: Correct answer: A. The cited official source confirms 3 nanometre. Therefore, option A is correct.
You have already explored a few exam notes. Upgrade for full explanations, premium revision lanes, and deeper quiz analysis.
Get Full Weekly Revision